Anritsu MP1900A Signal Quality Analyzer

Anritsu Offers PCI Express 7.0 Receiver Testing Solution

  • Anritsu has announced the introduction of a new testing solution for PCI Express 7.0 (PCIe Gen 7.0) receivers, integrated into its MP1900A Signal Quality Analyzer.

 

This test system aligns with the core specifications of the PCIe 7.0 standard and supports communication interfaces designed for data transfer rates up to 128 GT/s. This development addresses the validation needs of electronic components embedded in data center servers, particularly those used for artificial intelligence processing.

Automated Calibration and Signal Modeling

The solution generates constrained test signals incorporating added noise and jitter, simulating real-world physical disturbances in electrical connections. To simplify industrial validation processes, the software automates the calibration of test signals and jitter tolerance measurements.

This automation relies on interoperability with real-time oscilloscopes manufactured by the Japanese company’s technology partners. The goal of this integration is to reduce the operational workload for engineers facing increasingly complex test conditions, while also enabling signal conformity assessment from the earliest stages of hardware design.

Technical Specifications of the MP1900A Platform

The MP1900A analyzer is a Bit Error Rate Tester (BERT) used for characterizing receivers on various communication interfaces such as PCIe, USB, Thunderbolt, DisplayPort, and the 800 GbE standard.

For the PCIe 7.0 standard, the system generates test patterns using PAM4 (four-level pulse amplitude modulation) signals at a rate of 128 GT/s. The signal generation circuitry exhibits low intrinsic random jitter and a stable signal-to-noise ratio (SNDR), providing a reproducible measurement environment.

Through this functional extension and its participation in standardization groups, Anritsu aims to support certification testing by PCI-SIG, the organization responsible for validating the compliance of future PCIe-enabled devices.