Teledyne LeCroy's Summit T416 PCI Express 4.0 protocol analyzer

Teledyne LeCroy Releases PCI Express Gen 5 Protocol Analyzer

Teledyne LeCroy announced the support by Summit M5x PCIe Protocol Analyzer/Jammer the PCIe 4.0 specification as well as the next-generation PCIe 5.0 (32 GT/s) specification.

The Summit M5x PCIe is according to Teledyne Lecroy the first protocol analyzer to introduce jamming capabilities for NVMe and NVMe-MI protocols. Specifically, the Summit M5x jams transmissions between the root complex and endpoint while remaining within normal PCIe operating specifications. This compares to earlier PCIe jammers that created undesirable, out-of-spec latencies and retransmissions.

The Summit M5x can modify, replace, insert, or delete traffic between a PCIe root complex and endpoint to verify adherence to design specifications and identify potential errors in protocol behavior.
# Key Features of the PCIe 5.0-ready Summit M5x platform:

  • Supports transmission speeds up to 32 GT/s,
  • Monitors and analyzes emerging high-speed protocols built on the PCIe specification, such as Gen-Z and CCIX
  • Supports PCIe 4.0 at up to x16 link widths today and is designed to handle PCIe 5.0 at x8 link widths
  • Includes new probing methodology that eliminates the need for a traditional “interposer” type probe to interface with systems under test, which is ideal for server-based systems that utilize horizontal insertion
  • Features memory buffer that can be configured up to 128 GB
  • Controlled through USB or remotely through 1000-BaseT Ethernet
  • Can synchronize with other high-speed protocol analyzers from Teledyne LeCroy using CrossSync functionality, which enables time‐aligned packet traffic as well as cross triggering from multiple high‐speed serial busses for design, debug, and validation across bridges.

The Summit M5x PCIe Protocol Analyzer/Jammer is capable of capturing, decoding, modifying, and describing virtualized systems in a multitude of configurations. The CATC Trace View, along with the recently added spreadsheet view, NVMe queue-characterization tables, and LTSSM state views, helps to determine how well devices and systems are behaving in real-world environments. The BitTracer option, which records the bytes exactly as they traverse the link, gets developers down to the byte level to see traffic just before and after deskew. This allows for the debugging of PHY-layer problems and combines logic-analyzer features with a decoded protocol-analyzer view.

The Summit M5x features the latest in storage-protocol decoding including NVM Express (NVMe), SATA Express, SCSI Express, and others. It supports the latest in NVMe management technology described in the NVM Express Management Interface (NVMe-MI) protocol specification. For example, Summit analyzers can simultaneously capture in-band (PCIe bus) and out-of-band (SMBus) protocol traffic. In addition, a new hardware-extended recording mode for NVMe applications aids in debugging difficult-to-find SSD anomalies. Finally, communications between applications using the Trusted Computing Group’s Enterprise and Opal security can be decoded to confirm accurate data transmission.