- Marvin Test Solutions (MTS) has completed its range of boards with a user-programmable FPGA circuitry with the GX3800e series PXI module.
- This card in PXIe 3U format has a 400-pin FMC slot according to the VITA 57.1 standard.
- The GX3800e card features the Altera Cyclone V GX FPGA component that supports up to 3.125 Gbps xvr data rates and integrates more than 300,000 logic elements and 12.2 KB of memory.
It is possible to integrate a user-specific interface module or any other on-the-shelve FMC module. This makes it possible to design an instrument specifically adapted to an analog or digital test application.
The FPGA program is designed using Altera’s Quartus software or Quartus Prime Lite royalty-free tools. Altera’s Quartus software makes it possible to manage a complete FPGA design flow: graphic input or HDL description (VHDL or verilog) of digital architecture, simulation, synthesis and implementation on a reprogrammable target.
Almost all FPGAs rely on external devices or physical interfaces (PHY) to exchange with their external environment or the unit under test. This extends the FPGA’s limited input/output capabilities: most often mainly digital and very few, if any, analog.
The implementation of these physical interfaces generally requires the use of external interface cards that are adapted to the specificities of the supplier’s FPGA module.
The FMC (FPGA Mezzanine Card) format based on the VITA 57 standard is an alternative to supplier-specific solutions by offering standard physical and electrical interfaces to FPGAs. This allows the use of a standard mezzanine card portfolio on the market using a standardised interface method via a pre-defined connector.
VITA 57 defines the specifications of the mezzanine I/O module with connection to the FPGA or any other device with reconfigurable I/O.
Main features
The MTS GX3800e’s 400 pin FMC interface features 80 differential pairs, 4 differential clocks, (10) 3.125 Gbs xcvrs, two xcvr clocks, an I2C control interface, JTAG bus, and power / gnd connections. The FPGA device supports up to eight phase lock loops for clock synthesis, clock generation and for support of the I/O interface. Additional module resources include: 64M x 32 of DDR memory, 32M x 16 of flash memory (for defined core functions), Programmable clock generators, DMA controller.
The module has access to all of the PXI Express bus resources allowing the user to create a custom instrument which incorporates all of the PXI Express bus resources.
FPGA design and control
Control and access to the FPGA is provided via the GX3800e’s driver which includes DMA and interrupt support, tools for downloading the compiled FPGA code, and register read and write functionality. The GX3800e’s unique architecture partitions the PCIe interface separately from the user FPGA – eliminating the need for the user to incorporate the PCIe interface as part of his or her overall FPGA design. Access to the user FPGA is via an internal address and data bus with predefined registers which are supported by the module’s software driver and an interactive UI. The result is a simplified design / integration process since both the PCIe bus interface and associated software driver are known, tested entities.
The board is supplied with the GXFPGA library, a software package that includes a virtual instrument panel, and a Windows 32/64-bit DLL driver library and documentation. The virtual panel can be used to interactively program and control the instrument from a window that displays the instrument’s current settings and status. In addition, interface files are provided to support access to programming tools and languages such as ATEasy®, LabVIEW, LabVIEW/Real-Time, C/C++, Microsoft Visual Basic®, Delphi, and Pascal.
Once the user has compiled the FPGA design, the configuration file can be loaded directly into the FPGA or via on-board flash memory.
A separate software package – GtLinux – provides support for Linux 32/64 operating systems.
