- Teradyne and Tokyo Electron have developed an integrated testing solution dedicated to screening microelectronic components using the KGD (Known Good Device) methodology.
- This test cell targets the production of chips for artificial intelligence (AI) and data centers.
The evolution of microelectronics toward chiplet-based architectures involves integrating multiple chips (or dies) within a single package in a 2.5D or 3D configuration. In this type of complex assembly, the failure of a single individual component leads to the rejection of the entire structure. The KGD screening process is therefore used upstream of final encapsulation to verify the viability of each individual chip, in order to ensure the final yield and stabilize high-volume production.
Hardware Integration and Thermal Management
The proposed test cell combines two industrial pieces of equipment: Teradyne’s UltraFLEXplus automated test platform and Tokyo Electron’s Prexa SDP (Singulated Device Prober) probe positioning system.
During the testing cycle, Teradyne’s instruments execute the digital performance test sequences, while Tokyo Electron’s system handles the physical manipulation of components, temperature control, and heat dissipation required by the latest generation of processors. The cell’s architecture is based on an open ecosystem model, allowing foundries, fabless design companies, and OSATs to adapt third-party test boards, manipulators, or interface technologies.
Commercial Availability
According to Shannon Poulin, president of the semiconductor testing group at Teradyne, combining these two pieces of equipment provides a solution directly applicable to production lines for addressing the power density and thermal regulation constraints imposed by current logic circuits. This joint solution is already commercially available for evaluating individual chips before their integration into complex packages.
