Prodigy PGY-PCIeGen3/4-PA PCI Express analyzer

Prodigy offers the PGY-PCIeGen3/4-PA PCI Express analyzer

  • Prodigy Technovations offers the PGY-PCIeGen3/4-PA PCIe protocol analyzer for the development and validation of the PCIe interface for the M.2, U.2 and Embedded PCIe buses.
  • This analyzer identifies problems in the implementation of the PCI Express protocol layers.

The PGY-PCIeGen3/4-PA protocol analyzer supports 2.5, 5.0, 8.0 and 16GT/S speeds. In particular, it can simultaneously observe and decode PCI Express traffic from 2.5GT/S to 16GT/S. It supports protocol decoding and analysis of TS1, TS2, DLLP and TLP packets. It also provides a detailed view of LTSSM allowing designers to visualize PCIe state machine transitions.

PGY-PCIeGen3/4-PA software has capabilities to decode and analyze PCIe traffic over long traces. This allows for faster debugging time. In addition, designers have the ability to select and view the parameter of interest in the TS1, TS2, DLLP or TLP packet.

It also provides separate views of the decoding and analysis of exchanged configuration packets. The GUI provides several floating windows and the ability to view the content of the observed packet.

The LTSSM analysis function, included in the software, provides a graphical representation of the different protocol layer states as well as information about the substates.

The PGY-PCIeGen3/4-PA protocol analyzer has a memory depth of 64 GB making it possible to capture x4 link traffic. The analyzer also supports protocol packet content triggering and offers multi-level if-then-elseif triggering. This makes it possible to capture protocol details around the trigger condition and monitor the PCIe bus over a longer period of time.

# Key features of the PGY-PCIeGen3/4-PA PCIe Gen3/4 protocol analyzers:

  • Simultaneous analysis of 2.5, 5, 8 and 16GT/S protocol traffic
  • Acquisition memory management to capture protocol traffic using triggers, segmented memory, ring buffer and hardware filters
  • Software for long capture analysis with LTSSM view
  • Active M.2, U.2 interposer boards and custom solder probes
  • Simple and advanced triggering based on TS1, TS2, DLLP and TLP protocol packet content