- The PCI-SIG consortium, responsible for developing and managing the PCIe specifications, has selected Anritsu’s Signal Quality Analyzer-R MP1900A to implement PCI Express (PCIe) serial bus link conformance testing.
- The MP1900A tester was selected to perform PCIe 3.0/4.0 link equalization (Link EQ Test) and receiver jitter tolerance (Rx Test) tests.
Since the release of the PCIe 1.0 specification in 2003, the PCI Express bus has offered twice the data rates of the previous version. The PCIe 4.0 specification currently offers a transmission speed of 16 Gbps/lane. While PCIe 5.0, the latest revision of the serial bus standard for expansion cards on a computer, promises a transfer capacity of 32 gigabits per second per unidirectional channel or more than one terabit per second on the 16-channel bidirectional interface.
The PCI Express architecture has thus become an indispensable interface for PCs, communication equipment and servers requiring ever higher data transmission rates.
The PCI-SIG (Peripheral Component Interconnect Special Interest Group) is the industry consortium responsible for specifying the PCI (Peripheral Component Interconnect), PCI-X and PCI Express computer buses. It holds quarterly compliance workshops to certify PCIe devices. To meet the growing demand for testing more and more devices, the PCI-SIG has established a permanent test environment that uses test solutions from qualified vendors. Anritsu’s Signal Quality Analyzer-R MP1900A is part of its testing arsenal.
Features of the Signal Quality Analyzer-R MP1900A
The Signal Quality Analyzer-R MP1900A can support the testing of PCI Express interfaces from version 1.0 (2.5 Gbit/s) to version 5.0 (32 Gbit/s). It will be updated to support PCI Express version 6.0 (64 Gbit/s). The analyzer is also compatible with oscilloscopes from the three major manufacturers to automate receive (Rx) test procedures up to PCI version 5.0 and the future PCIe 6.0 specification.
The Signal Quality Analyzer-R MP1900A is a multi-channel bit error rate tester (BERT). It incorporates a pulse pattern generator (PPG) that produces a residual jitter of 115 fs rms, an error detector (ED) with the sensitivity to provide an eye diagram of 15 mV (typical) amplitude, and a jitter generator (SJ, RJ, SSC, BUJ). In addition to the CM-I/DM-I functions, it supports analysis of Link Training and LTSSM (Link Training Status Machine) functions. This analyzer enables compliance testing, margin testing and troubleshooting.